And here it is, at long last. A rough, preliminary sketch of the new instruction set architecture for a next-generation successor to my S16X4 #stack CPU family.
This is a proper #Forth CPU ISA design. A bit CISCy, though, but I think it's usable.
This entry was edited (1 year ago)
Devine Lu Linvega
in reply to Vertigo #$FF • • •