I’ve been learning some Verilog, and attempting to rewrite the Pocket Varvara core.
The design is a little simpler than before. It’s also a little faster and higher res now
It still doesn’t do everything the PipelineC version of core can do, but this rewrite may prove worthwhile in the end. Lots of catching up to do still 🙂
The screen test ROM is looking pretty good though, except for the top and left edge
Devine Lu Linvega
in reply to tsalvo • • •tsalvo
in reply to tsalvo • • •Bunnymark:
305 🐰 (existing 0.0.4 core)
355 🐰 (WIP 0.0.5 core)
#uxn #varvara #AnaloguePocket
Devine Lu Linvega
in reply to tsalvo • • •mcc
in reply to Devine Lu Linvega • • •Devine Lu Linvega
in reply to tsalvo • • •~rabbits/uxn11 (main): etc/screen.bounds.tal - sourcehut git
git.sr.httsalvo
in reply to Devine Lu Linvega • • •