Some more progress on sprites! The 2bpp mode is working much better now, but I still have lots of weird drawing bugs. It’s getting there slowly though 😀

#AnaloguePocket #uxn #varvara #fpga

At the SVFIG #Forth day in November 2023, I will be giving a talk on the #j1 family of processors.

https://www.meetup.com/sv-fig/events/296503788/

#fpga

SVFIG Forth Day In Person and Zoom --- Third Saturday!

**WE NEED SPEAKERS!** **=+=+** Join us on Zoom or in person at Stanford for our annual Forth Day! We'll have the opportunity to meet in person enjoy lunch

^Meetup

I am interested in building a #uxn cpu on an #fpga.
I have already built #Mecrisp #Forth on the #PicoIce.
A Uxn cpu is just a slightly different stack machine.
Maybe I will eventually build an entire Varvara computer on an FPGA.

@neauoire
@rek

https://forth.pythonlinks.info/hana-uxn

Hana UXN

Hana UXN will support the UXN opcodes.

^{forth.pythonlinks.info}

My verilog implementation of a #uxn CPU just executed its first program! It is incredibly basic (#01 #02 ADD BRK), but I am still quite happy that it works at all.

The CPU is a microprogrammed processor using a custom microcode format, that allows easy access to stack operations. Here is the microcode for the ADD instruction:

src -> a
src -> b
alu.add -> src

The microcode for LIT is slightly more complex:

@BRK keep byte
pc -> mem.addr
mem.8 -> src
pc -> a
one -> b
alu.add -> pc

#fpga